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White Electronic Designs
WV3EG265M72EFSU-D4
ADVANCED*
1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA
FEATURES
Unbuffered 200-pin (SO-DIMM), small-outline, dualin-line module Fast data transfer rate: PC-2100, and PC-2700 Clock speeds of 133MHz, and 166MHz Supports ECC error detection and correction VCC = VCCQ = +2.5V 0.2V(133 and 166MHz) Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency: DDR 266 (2, 2.5 clock), DDR333 (2.5 clock) Programmable Burst Length (2, 4, 8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh, 7.8s refresh interval (8K/64ms refresh) Serial presence detect (SPD) with EEPROM Dual Rank Leaded & lead-free/RoHS compliant Gold edge contacts JEDEC standard 200 pin, small-outline, SO-DIMM package * PCB height option: 31.75 mm (1.25")
* This product is under development, is not qualified or characterized and is subject to change or cancellation without notice.
DESCRIPTION
The WV3EG265M72EFSU is a 2x64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eighteen 64Mx8 DDR SDRAMs in FBGA packages mounted on a 200 pin FR4 substrate.
NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option
OPERATING FREQUENCIES
DDR333@CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266@CL=2 133MHz 2-2-2 DDR266@CL=2.5 133MHz 2.5-3-3
May 2006 Rev. 0
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PIN CONFIGURATION
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 51 VSS 101 A9 151 DQ42 1 VREF 2 VREF 52 VSS 102 A8 152 DQ46 53 DQ19 103 VSS 153 DQ43 3 VSS 4 VSS 54 DQ23 104 VSS 154 DQ47 5 DQ0 55 DQ24 105 A7 155 VCC 6 DQ4 56 DQ28 106 A6 156 VCC 7 DQ1 57 VCC 107 A5 157 VCC 8 DQ5 58 VCC 108 A4 158 NC 9 VCC 59 DQ25 109 A3 159 VSS 10 VCC 60 DQ29 110 A2 160 NC 11 DQS0 61 DQS3 111 A1 161 VSS 12 DM0 62 DM3 112 A0 162 VSS 13 DQ2 63 VSS 113 VCC 163 DQ48 14 DQ6 64 VSS 114 VCC 164 DQ52 65 DQ26 115 A10 165 DQ49 15 VSS 16 VSS 66 DQ30 116 BA1 166 DQ53 17 DQ3 67 DQ27 117 BA0 167 VCC 18 DQ7 68 DQ31 118 RAS# 168 VCC 19 DQ8 69 VCC 119 WE# 169 DQS6 20 DQ12 70 VCC 120 CAS# 170 DM6 21 VCC 71 CB0 121 CS0# 171 DQ50 22 VCC 72 CB4 122 CS1# 172 DQ54 23 DQ9 73 CB1 123 NC 173 VSS 24 DQ13 74 CB5 124 NC 174 VSS 25 DQS1 75 VSS 125 VSS 175 DQ51 26 DM1 76 VSS 126 VSS 176 DQ55 27 VSS 77 DQS8 127 DQ32 177 DQ56 78 DM8 128 DQ36 178 DQ60 28 VSS 29 DQ10 79 CB2 129 DQ33 179 VCC 30 DQ14 80 CB6 130 DQ37 180 VCC 31 DQ11 81 VCC 131 VCC 181 DQ57 32 DQ15 82 VCC 132 VCC 182 DQ61 83 CB3 133 DQS4 183 DQS7 33 VCC 34 VCC 84 CB7 134 DM4 184 DM7 35 CK0 85 NC 135 DQ34 185 VSS 36 VCC 86 NC 136 DQ38 186 VSS 37 CK0# 87 VSS 137 VSS 187 DQ58 38 VSS 88 VSS 138 VSS 188 DQ62 39 VSS 89 NC 139 DQ35 189 DQ59 40 VSS 90 VSS 140 DQ39 190 DQ63 41 DQ16 91 NC 141 DQ40 191 VCC 42 DQ20 92 VCC 142 DQ44 192 VCC 43 DQ17 93 VCC 143 VCC 193 SDA 44 DQ21 94 VCC 144 VCC 194 SA0 45 VCC 95 CKE1 145 DQ41 195 SCL 46 VCC 96 CKE0 146 DQ45 196 SA1 47 DQS2 97 NC 147 DQS5 197 VCCSPD 48 DM2 98 NC 148 DM5 198 SA2 49 DQ18 99 A12 149 VSS 199 NC 50 DQ22 100 A11 150 VSS 200 NC
WV3EG265M72EFSU-D4
ADVANCED
PIN NAMES
Symbol A0-A12 BA0, BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0, CK0# CKE0-CKE1 CS0#-CS1# RAS# CAS# WE# DM0-DM8 VCC VSS VREF VCCSPD SDA SCL SA0-SA2 NC Description Address input Bank Address Data Input/Output Check Bits Data Strobe Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Input Write Enable Data Write Mask Power Supply Ground SSTL_2 reference voltage Serial EEPROM Positive Power Supply Input/Output: Serial PresenceDetect Data Serial Clock Presence Detect Address Input No Connect
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WV3EG265M72EFSU-D4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1# CS0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA0, BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE# DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ
DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2 DDR2 SDRAM X 2
DQS4 DM4 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DM5 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS6 DM6 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS7 DM7 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ
120
CK0 CK0#
PLL
BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs CKE1: DDR SDRAMs WE#: DDR SDRAMs VCC VREF VSS DDR SDRAMs DDR SDRAMs DDR SDRAMs SA0 SA1 SA2 SCL WP VCCSPD SPD/EEPROM SERIAL PD SDA A0 A1 A2
NOTE: All resistor values are 22 5% unless otherwise specified.
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WV3EG265M72EFSU-D4
ADVANCED
DC ELECTRICAL CHARACTERISTICS
PARAMETER/CONDITION Supply Voltage DRR266/DDR333 (nominal VCC 2.5V) I/O Supply Voltage DRR266/DDR333 (nominal VCC 2.5V I/O Reference Voltage I/O Termination Voltage Input Logic High Voltage Input Logic Low Voltage Input voltage level, CK and CK# Input differential voltage, CK and CK# Input crossing point voltage, CK and CK# Addr CAS#, RAS#, WE# CS#, CKE Input leakage current CK, CK# DM Output leakage current Output high current (normal strength) VOUT = v +0.84V Output high current (normal strength) VOUT = VTT - 0.84V Output high current (half strength) VOUT = VTT - 0.45V Output high current (half strength) VOUT = VTT - 0.45V SYMBOL VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) MIN 2.3 2.3 0.49 x VCC VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.3 0.3 -36 II -18 -10 -4 -10 -16.8 16.8 -9 9 MAX 2.7 2.7 0.51 x VCC VREF + 0.04 VCC + 0.30 VREF - 0.15 VREF + 0.30 VREF + 0.60 VREF - 0.60 36 18 10 4 10 UNITS V V V V V V V V V A A A A A mA mA mA mA Notes
1 2
3
IOZ IOH IOL IOH IOL
Notes: 1 VREF is expected to equal to 0.5*VCCQ of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-2 percent of the DC value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level of CK#.
ABSOLUTE MAXIMUM RATINGS
Symbol VIN, VOUT VCC, VCCQ VREF TSTG TA PD IOS Parameter Voltage on VCC pin relative to VSS Voltage on VCC & VCCQ supply relative to VSS Voltage of VREF supply relative to VSS Storage Temperature Operating temperature Power dissipation Short circuit output current Value -0.5 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 0 ~ 70 18 50 Units V V V C C W mA
Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceed. Functional ioeration should be restricted to recommended operation conditions. Exposing to higher than recommended voltage for extended periods of time could affect device reliability.
May 2006 Rev. 0
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WV3EG265M72EFSU-D4
ADVANCED
AC OPERATING CONDITIONS
Parameter AC Input High (Logic 1) Voltage AC Input High (Logic 0) Voltage Input Differential Voltafe, CK and CK# inputs Input Crossing Point Voltage, CK and CK# input Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF + 0.31 0.7 0.5*VCC - 0.2 Max VREF - 0.31 VCC + 0.6 0.5*VCC + 0.2 Unit V V V V
INPUT/OUTPUT CAPACITANCE
TA=25C, f=100MHz Parameter Input capacitance (A0~A12, BA0~BA1, RAS#, CAS#, WE#) Input capacitance (CKE0, CKE1) Input capacitance (CS0# - CS1#) Input capacitance (CLK0, CLK0#) Input capacitance (DM0~DM8) Input capacitance (DQ0~DQ63), (CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 Min 31 17.5 17.5 6 11 11 Max 49 26.5 26.5 7.5 13 13 Unit pF pF pF pF pF pF
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VCC, VCCQ = +2.5V 0.2V
WV3EG265M72EFSU-D4
ADVANCED
ICC SPECIFICATIONS AND CONDITIONS
MAX SYM ICC0* PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH BURST CURRENT: SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands tREFC = tRFC (MIN) DDR333 @CL=2.5 1,270 DDR266 @CL=2 1,180 DDR266 @CL=2.5 1,180 UNITS mA
ICC1* ICC2P** ICC2F**
1,540 370 820
1,450 370 820
1,450 370 820
mA mA mA
ICC3P** ICC3N**
820 1,090
820 1,090
820 1,090
mA mA
ICC4R* ICC4W*
1,585 1,675
1,450 1,495
1,450 1,495
mA mA
ICC5** ICC6** ICC7*
3,970 370 3,565
3,790 370 3,250
3,790 370 3,250
mA mA mA
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different. *: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition.
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WV3EG265M72EFSU-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
VCC = VCCQ = +2.5V 0.2V AC CHARACTERISTICS PARAMETER Row cycle time Refresh row cycle time Row active RAS# to CAS# delay Row precharge time Row active to row active delay Write recovery time Last data in to READ command Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK# Output data access time from CK/CK# Data stobe edge to output data edge Read preamble Read postamble CK to vaild DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge to CK rising-hold time DQS-in high level width DQS-in low level width Address and control input setup time (fast) Address and control input hold time (fast) Address and control input setup time (slow) Address and control input hold time (slow) Data-out high impedance time from CK/CK# Data-out low impedance time to CK/CK# Mode register set cycle DQ & DM setup time to DQS DQ & DM hold time to DQS Control & address input pulse width DQ & DM input pulse width Exit self refresh to non-read command CL = 2.5 CL =2 SYMBOL
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR
335 MIN 60 72 42 18 18 12 15 1 6 7.5 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.75 0.75 0.8 0.8 -0.70 -0.70 12 0.45 0.45 2.2 1.75 75 MAX MIN 65 75 45 20 20 15 15 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 1.0 1.0 -0.75 -0.75 15 0.5 0.5 2.2 1.75 75
262 MAX MIN 65 75 45 20 20 15 15 1 7.5 10 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 1.0 1.0 -0.75 -0.75 15 0.5 0.5 2.2 1.75 75
265 MAX
UNITS tCK ps ps tCK ns ns ns ns ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns
70K
120K
120K
tCK (2.5) tCK (2) tCH tCL tDQSCK
tAC
tDQSQ
tRPRE tRPST
tDQSS
tWPRES tWPRE
12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25
12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25
12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25
tDSS
tDHS tDQHS TDQSL tISF tIHF tISS tIHS tHZ tLZ tMRD tDS tDH tIPW tDIPW tXSNR
+0.70 +0.70
+0.75 +0.75
+0.75 +0.75
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page
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WV3EG265M72EFSU-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
VCC = VCCQ = +2.5V 0.2V AC CHARACTERISTICS PARAMETER Exit self regresh to read command Refresh interval time Output DQS vaild window Clock half period Data hold skew factor DQS write postamble Active Read with auto precharge command Auto precharge Write recovery + Precharge time SYMBOL tXSRD tREFI tQH tHP tQHS tWPST tRAP tRAL 0.4 18 tWR/tCK + tRP/tCK tHP-tQHS tCLmin or tCHmin 0.55 0.6 0.4 20 tWR/tCK + tRP/tCK MIN 200 7.8 tHP-tQHS tCLmin or tCHmin 0.75 0.6 0.4 20 tWR/tCK + tRP/tCK 335 MAX MIN 200 7.8 tHP-tQHS tCLmin or tCHmin 0.75 0.6 262 MAX MIN 200 7.8 265 UNITS MAX tCK s ns ns ns ns ns tCK
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
May 2006 Rev. 0
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White Electronic Designs
WV3EG265M72EFSU-D4
ADVANCED
ORDERING INFORMATION FOR D4
Part Number WV3EG265M72EFSU335D4xxx WV3EG265M72EFSU262D4xxx WV3EG265M72EFSU265D4xxx Speed 166MHz/333Mbps 133MHz/266Mbps 133MHz/266Mbps CAS Latency 2.5 2 2.5 tRCD 3 2 3 tRP 3 2 3 Height* 31.75 (1.25") MAX 31.75 (1.25") MAX 31.75 (1.25") MAX
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
200-PIN DDR SO-DIMM DIMENSIONS
FRONT VIEW
67.75 (2.667) 67.45 (2.656) 3.80 (0.150 ) MAX
4.10 (0.161) 2X 3.90 (0.154) 31.90 (1.256) 31.60 (1.244) 20.00 (0.787) TYP 6.00 (0.236) 2.55 (1.00) 1.10 (0.043) 0.90 (0.035) 1.00 (0.039) TYP 0.45 (0.018) TYP 63.60 (2.504) TYP 0.60 (0.024) TYP
1.80 (0.071) (2X)
2.15 (0.085
PIN 199
PIN 1
BACK VIEW
PIN 200
4.2 (0.165) TYP 47.40 (1.866) TYP 11.40 (0.449) TYP
PIN 2
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2006 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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WV3EG265M72EFSU-D4
ADVANCED
PART NUMBERING GUIDE
WV 3 E G 2 65M 72 E F S U xxx D4 x x x
WEDC MEMORY (SDRAM) DDR GOLD DUAL RANK DEPTH (x64 "5"indicates with PLL) BUS WIDTH COMPONENT WIDTH x8 FBGA 2.5V UNBUFFERED SPEED (Mb/s) PACKAGE 200 PIN INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = MICRON) (S = SAMSUNG) (N = NANYA) G = RoHS COMPLIANT (Add "G" for RoHS,leave "blank" for leaded)
May 2006 Rev. 0
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Document Title
WV3EG265M72EFSU-D4
ADVANCED
1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, with PLL, FBGA DRAM DIE OPTIONS: * SAMSUNG: C-Die * MICRON: T27Z: D-Die, will move to T37Z:F Q2'06 * NANYA: B-Die
Revision History Rev #
Rev 0
History
Created
Release Date
May 2006
Status
Advanced
May 2006 Rev. 0
11
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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